This invention relates to a circuit for protecting voltage-sensitive components in an integrated circuit from an electrostatic discharge or other source of potentially damaging overvoltage. In particular, this invention relates to a circuit for protecting voltage-sensitive components or circuits in an integrated circuit (IC) which are insufficiently protected by conventional electrostatic discharge (ESD) clamps.
In order to protect an integrated circuit from a potentially damaging electrostatic discharge, it is commonplace to provide an ESD clamp between the power supply rail and ground to which the integrated circuit is coupled. During an ESD event, an ESD clamp placed across the power supply of a circuit provides a safe current path through the chip and around the circuit being protected. When an ESD events occurs, the ESD clamp acts to conduct the electrostatic charge to ground, thus dissipating the overvoltage at the power supply rail. The ESD clamp is configured to trigger when an ESD event is detected at the supply rail and then subsequently limit the voltage to below the lowest failure voltage of all the components in the circuit. In this way the designer of the circuit can guarantee that none of the components in the circuit will be damaged during an ESD event.
Typically, ESD clamps that clamp to higher voltages during an ESD event are also tolerant to higher voltages during normal operation. Conversely high performance clamps that can clamp to a lower voltage, and therefore protect more sensitive components, are generally tolerant only up to lower power supply voltages. It is for some circuits possible to design power supply clamps with high power supply voltage tolerance and low clamping voltage but these clamps are significantly larger and have a higher leakage current during normal operation.
In some instances it can be useful to design circuits which are powered from relatively high voltage power supplies yet contain high performance components (such as thin oxide transistors, low voltage diodes, n-well resistors, thin gate oxide capacitors or other low voltage components) that cannot be protected by a high voltage clamp. During normal operation the circuit is configured such that these high performance components operate at voltages within their safe operating range, but during an ESD event it is not possible to ensure that the maximum clamped voltage is not applied across any given component.
This can occur in practice when power supply clamps suitable for thick oxide (double oxide or DO) MOSFETs are used to protect circuits that comprise thin oxide (single oxide or SO) MOSFETs, or circuits comprising a mix of SO and DO transistors.
Conventionally, low voltage components are often protected simply by adding resistors between the components and the power supply, thus limiting the current through and the voltage across those components during the ESD event. However, in many circuits such a resistor configuration cannot be used as they limit the current through the components during normal operation and can prevent the circuit from operating correctly.
There is therefore a need for a circuit arrangement that can protect voltage-sensitive components during an ESD event in a circuit having a relatively high voltage power supply.